A need continues to grow for more complex semiconductor (SC) based devices and circuits able to operate at higher and higher frequencies and handle increasing amounts of power and have lower unit cost. Many of these requirements create conflicting demands on the associated semiconductor device and integrated circuit (IC) design and manufacturing technology. For example, and not intended to be limiting, most SC devices and ICs are fabricated in and/or on substrate wafers, usually but not always single crystal SC wafers, which are then cut up (“singulated”) into the individual devices or ICs. The manufacturing cost can be reduced by using larger and larger wafers, since more devices and ICs can be produced at the same time on larger wafers. However, to avoid undue wafer breakage, the wafer thickness must be increased as the wafer diameter is increased. With thicker wafers, the resulting IC or SC die thickness increases, and it becomes more difficult to remove heat from the devices or ICs. A further complication is the desire to be able to provide additional wiring on the SC die or IC and to include further interconnection layers and passive devices such as inductors, capacitors, and interconnections as a part of the SC die or IC. As used herein, the words “interconnection(s)”, “interconnection layers” and “interconnect levels” and the like, singular or plural, are intended to couple different connection points on or above the SC surface and to include any type of passive components.
If only one surface of the SC die or IC is available for fabricating semiconductor devices and interconnections, the desired degree of complexity may not be achievable with present day structures and fabrication techniques. Further, as operating speed and power handling increase, the problems of efficient heat removal from the device die or IC become more and more difficult. Thus, there is a strong desire to be able to provide interconnections on the rear surface as well as the front surface of the devices or ICs, and to facilitate efficient heat transfer from the front surfaces where the active devices are typically located to the rear surface of the die or IC, without compromising mechanical robustness of the wafers during manufacture.
It is known to use conductor filled vias through the SC wafers as a means of providing electrical and thermal connections between the front and rear surfaces of the wafer and resulting individual device and IC die. These conductor filled vias are referred to as “through-substrate-vias” or “through-semiconductor-vias” and abbreviated as “TSV” (singular) or “TSVs” (plural). However, the desire to use larger diameter wafers for cost efficient manufacturing and at the same time provide highly conductive TSVs for electrically and thermally coupling the front and rear faces of the wafer substrate and resulting die are in conflict. The thicker the wafers, the more difficult it is to etch and fill the TSVs with conductors and the larger the amount of wafer area that must be devoted to such vias. Thus, thicker wafers mean larger TSVs and wasted device and IC surface area, thereby lowering the device and IC packing density on the wafer and increasing the cost of the resulting devices and ICs. Conversely, trying to use large diameter thin wafers so as to maintain the device area packing density reduces the mechanical stability of the wafers. It is well known that thin wafers break more easily, thereby reducing the manufacturing yield and increasing the cost of the resulting die and ICs. Thus, a need continues to exist for improved SC device and IC structures and fabrication techniques that facilitate providing minimal area TSVs for back-side interconnections and/or efficient heat removal without compromising mechanical stability of the wafers during manufacturing.